1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, determine optimal device characteristics, or produce small production runs.
2. Background Art
Some semiconductor processing steps create radial differences across the wafer. For example, when performing Chemical-Mechanical Polishing (CMP) of the surface of a semiconductor wafer, the portion of the semiconductor wafer towards the outer circumference of wafer will be ground more than the inner portion of the semiconductor wafer. Similarly, during a Reactive Ion Etch (RIE) of the gate stack, the gates formed at the outer periphery of the semiconductor wafer will be etched more then the gates formed near the center of the semiconductor wafer. Consequently, the gates at the outer periphery of the semiconductor wafer will have a smaller width than the gates at the center of the semiconductor wafer. Both of these radial processing effects will cause radial differences in device characteristics between devices formed at the center of the wafer and devices formed near the outer periphery of the wafer.
Additionally, as the semiconductor industry progresses towards very large wafer sizes, there will be more waste during the small batches that are used to determine optimal device characteristics. For example, with large wafer sizes, a small company may only need to order enough chips to fill 20 to 50 wafers. To determine optimal device characteristics, several runs through the process will usually be performed with a few wafers. Each of these wafers will have something modified such as gate width or composition of the gate dielectric that is expected to change one or more device characteristics. Each of devices on the wafers are compared to determine which of the devices have the optimal device characteristics for the current application. However, these few wafers and the processing time and steps performed to complete them can be relatively expensive.
Moreover, as the semiconductor industry converts to large wafer sizes, small batches of specialty chips, especially those made for a small chip designer, can become relatively expensive. During production runs for a small chip designer, it is usually unclear what device characteristics are appropriate for the designer“s chips. Consequently, several wafers will be run through the production line, with each wafer producing devices having different characteristics. The small chip designer can then choose the best chips to be packaged. Unfortunately, this process generates excessive waste, is therefore costly, and takes quite a bit of time.
Therefore, without a way to reduce or eliminate radial processing effects, to determine optimal device characteristics, or to produce small batches of varied semiconductor devices, semiconductor devices built near the center of the semiconductor wafer will have different characteristics than devices built near the periphery of the wafer, and there will be higher cost and more waste when performing prototyping to determine optimal device characteristics and to produce small batches of chips.